It has been known for many years that extremely high voltages (e.g. 10,000 volts or greater) can develop in an integrated circuit (IC) due to the build-up of static charge. Electrostatic discharge (ESD) refers to the phenomena whereby a high energy electrical discharge of current is produced at the input and/or output nodes of an integrated circuit as a consequence of static charge build-up. Electrostatic discharge is a serious problem for semiconductor devices since it has the potential to disable or destroy the entire integrated circuit. Because ESD events occur most often across the junction of an input or output transistor, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuit elements. Ideally, an ESD protection device should be able to discharge an extremely large potential across any two pins of an IC in a nondestructive manner.
Previous technologies relied extensively upon a phenomena commonly known as "snap-back" for providing ESD protection. The difficulty with this approach is that the junction breakdown and bipolar snap-back phenomena are highly nonuniform, and also have a positive temperature coefficient for conduction. This results in a highly localized current conduction that makes these devices inherently weak and susceptible to localized junction damage. Device scaleability is also a problem because of the localized current conduction. Moreover, increasing the device size in these technologies does not necessarily improve the ESD performance.
Actually, the snap-back phenomena is a potentially valuable tool for ESD protection if the device experiencing snap-back can withstand the high energy levels without irreversible damage. The snap-back phenomena refers to the use of a junction breakdown to control current and voltage behavior in the manner of a voltage clamp. A snap-back device is designed to keep the voltage low enough to protect sensitive gate dielectrics. By way of example, n-channel devices were protected from irreversible damage in earlier technologies by distributing resistance within a diffusion layer. In other words, by spacing the metal-to-drain diffusion contact several microns away from the gate edge the drain diffusion introduced a significant resistance into the snap-back circuit. This distributed diffusion resistance provided a negative feedback to current crowding, thus increasing current conduction uniformity and raising ESD performance to more acceptable levels.
The problem with this approach is that many advanced semiconductor processes now utilize diffusions clad with titanium or a titanium alloy (e.g., titanium salicide). Alloying a metal such as titanium onto the diffusion regions has the effect of reducing the distributed resistance by at least an order of magnitude. The end result is that the snap-back behavior is no longer effective for ESD protection.
Another difficulty in designing ESD circuits is the demanding performance requirements which must be met. For example, one of the primary industry standards for measuring ESD robustness--MIL-STD-883C method 3015.7 Notice 8--requires ESD "zapping" for all possible pin and power supply combinations. In the past, ESD protection circuits have had difficulty in meeting these stringent military standard performance requirements while maintaining adequate noise immunity.
Therefore, what is needed is a robust electrostatic protection circuit which is capable of meeting the increased demands on product design performance. As will be seen, the present invention provides a ESD protection circuit which exceeds industry performance goals while maintaining noise immunity margins. In addition, the present invention provides for an inherently uniform current conduction process which may be utilized in a great variety of semiconductor processes--including those which utilize diffusions clad with titanium or a titanium alloy.